Porous silicon is a nanostructured material that may be composed of interconnected crystallites and pores having a dimension of 1-100 nm. Promising approaches for micron- and submicron-scale pattern formation in porous silicon have been reported using either lithography methods, which selectively mask the porous silicon removal or generation, or maskless localized treatments of silicon surfaces, which block or enhance porous silicon formation or dissolution. Among the specific techniques used include ion irradiation or implantation, electron beam lithography and irradiation, localized far-field or near-field illumination, dry-removal soft lithography, and lithography with a multilayer electrochemical resistant mask. The spatial resolution of these techniques may be limited by lithography tools or by the fragility and reactivity of porous silicon during formation or etching. As a result, a large-area fabrication method for producing nanoscale (<100 nm) patterned porous silicon is still lacking.
Patterned porous silicon structures are potentially useful for integrated optical and electronic applications. Specifically, the areas of extendability of copper (Cu) interconnects and low dielectric constant (low-k) insulators, novel approaches to interconnects, and the global interconnect problem have been identified as of immediate importance to continued progress in the semiconductor industry. One of the pathways to achieve low-k dielectrics is to incorporate pores into silicon oxide-based materials. A current solution is to create the porous low-k dielectrics first using, for example, spin-on organic polymeric materials, followed by dry etching to create vias and holes for subsequent gap fill with copper. However, the mechanical stability of the porous low-k material makes it susceptible to damage from etching and CMP. The integrity and the cleanliness of interconnect structures are of great concern as the semiconductor industry strives to extend the semiconductor technology roadmap beyond the 32 nm node.